1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a built-in self-test (BIST) circuit.
2. Description of the Related Art
One of the methods of performing a manufacturing test of a semiconductor integrated circuit having an embedded memory is to incorporate a built-in self-test circuit in the semiconductor integrated circuit and to perform a test of the memory device by using the self-test circuit. This built-in self testing method includes a comparator-type BIST and a compactor-type BIST. In the comparator-type BIST, a comparison between written data and read data with respect to a memory device is performed in the semiconductor integrated circuit, and the manufacturing test is performed by investigating whether the written data and the read data match with each other. On the other hand, in the compactor-type BIST, read data that is read from a memory device is compacted in the semiconductor integrated circuit, and the resultant compacted data is sent to a tester. Then, the manufacturing test is performed by comparing the compacted data with an expected value that is calculated in advance as a test result. In this case, a multiple input signature register (MISR), which is a modified version of a linear feedback shift register (LSFR), is generally used, as described in Paul H. Bardell, William H. McAnney, and Jacob Savir, “Built-in Test for VLSI: Pseudo Random Techniques, John Wiley&Sons, 1987.
In general, a test algorithm for a manufacturing test of a memory is developed in such a manner that a certain level of defect in a basic peripheral circuit, such as an address decoder and an input/output (I/O) circuit, can be detected as well as a cell array in a memory device, as in the case of a marching test.
However, for a circuit of an additional function other than such basic peripheral circuits, it is often the case that a detection of a defect in the circuit is unconsidered. For example, for a bit write enable circuit that controls a data write to a memory for each bit, a test is usually executed by setting the function to an enabled state in many cases in the marching test and the like, so that the function of the bit write enable circuit itself is not thoroughly tested.
In addition, a data pattern used in the test algorithm for the manufacturing test of the memory is generally a regular pattern such as a pattern in which all bits are “0”s or “1”s and a checkerboard pattern. For this reason, a data pattern applied to an input of a memory device is sometimes generated from the minimal data register in a BIST circuit to suppress a circuit size.
In this case, between even-numbered bit inputs of the memory device, for example, it is only possible to take a state of the same signal value because the data pattern is supplied from the same data register. Meanwhile, on a semiconductor integrated circuit, physical wirings connected to input terminals of a memory device, which is not adjacent to each other, may be passed around and placed adjacent to each other on the semiconductor integrated circuit, so that some even-numbered inputs may be adjacent to each other on the wiring. For this reason, in the case where a state can be only obtained with the same signal values during a test, even if a short defect occurs between wirings to be connected to even-numbered bit inputs, it is not possible to detect the short defect between the even-numbered bit inputs.
To cope with the above problem, a method is disclosed in U.S. Pat. No. 4,969,148 in which a switching circuit that switches an output of a memory device from a bit to an input of an adjacent bit is provided to build a test circuit such that a data input for a test is applied to the first one bit only. In this method, because the data of the memory is rewritten for each bit during the test, a reverse signal value is surely taken between arbitrary two bits, which makes it possible to detect a short defect between the wirings.
However, in the method disclosed in U.S. Pat. No. 4,969,148, at the time of performing a marching test, for example, because a test is performed in units of bit, instead of typical units of word, as many times as the number of addresses, the test time is increased as long as the multiple of the maximum number of bits.